Both Verilog and VHDL are very powerful design languages for FPGAs. Design at the RTL level produces a straightforward synthesis into FPGA gates. Performance of the two languages is comparable. Choice of which HDL to use is most affected by EDA tool availability and the need to exchange design data with other organizations or groups.
There are several varieties of microprocessor, DSP chips, and DSP cores that are suitable for test equipment design. The choice of which to use depends on cost, accuracy and throughput goals. DSP chip vendors supply libraries of standard DFT and filter algorithms. However using these libraries to create good system level performance requires extensive knowledge of the DSP mathematical foundations.